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Logic Synthesis and Verification Algorithms


Extreame Savings Item! Save 45% on the Logic Synthesis and Verification Algorithms by Springer at EMS Linux. MPN: bibliography, index. Hurry! Limited time offer. Offer valid only while supplies last. Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and


Product Description

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

Additional Information

Manufacturer:Springer
Brand:Springer
Part Number:bibliography, index
Publisher:Springer
Studio:Springer
MPN:bibliography, index
EAN:9780792397465
Item Weight:3.1 pounds
Item Size:1 x 10 x 10 inches
Package Weight:3.4 pounds
Package Size:7.32 x 1.56 x 1.56 inches

Logic Synthesis and Verification Algorithms by Springer

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Logic Synthesis and Verification Algorithms

Brand: Springer
Condition: New
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