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Management and Analysis of Bitstreams Generators for Xilinx FPGAs: analysis of FPGA configuration memory for Dynamic Reconfigurable architectures


Free Shipping Included! Management and Analysis of Bitstreams Generators for Xilinx FPGAs: analysis of FPGA configuration memory for Dynamic Reconfigurable architectures by VDM Verlag at EMS Linux. Hurry! Limited time offer. Offer valid only while supplies last. This work introduces the concepts used in analyzing the end product of the Xilinx FPGA bitstream generation toolchain, for the application of Dynamic


Product Description

This work introduces the concepts used in analyzing the end product of the Xilinx FPGA bitstream generation toolchain, for the application of Dynamic Reconfiguration methodologies, i.e. a particular set of tecniques used to change a portion of the FPGA hardware at runtime. By analyzing the bitstream files of single hw sections, the requirements enforced by the manufacturer can be verified by means of an automated SW - separated from Xilinx toolchain - described in the book. The insight into configuration memory gained from the analysis of bitstreams has been further exploited to implement advanced tools for dynamic reconfiguration, such as analysis of area conflicts in the evolution of the configuration over time, or possible bitstream relocation position computation. This book illustrates the algorithms and methodologies used for extracting information from bitstream files, verifying constraints and perform further analysis in light of dynamic reconfiguration capabilities of the FPGA.

Additional Information

Manufacturer:VDM Verlag
Publisher:VDM Verlag
Studio:VDM Verlag
EAN:9783639205862
Item Size:0.38 x 8.66 x 8.66 inches
Package Weight:0.66 pounds
Package Size:5.91 x 0.38 x 0.38 inches

Management and Analysis of Bitstreams Generators for Xilinx FPGAs: analysis of FPGA configuration memory for Dynamic Reconfigurable architectures by VDM Verlag

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Management and Analysis of Bitstreams Generators for Xilinx FPGAs: analysis of FPGA configuration memory for Dynamic Reconfigurable architectures

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